Synchronous integrated circuits operate according to an externally supplied clock signal. Internal circuit functions are performed in response to transitions of the clock signal. A detection circuit, or buffer, is typically provided to monitor the clock input signal and produce an output signal indicating the detection of a transition in the clock signal. These detection circuits can also produce complimentary output signals where one signal follows the clock signal, and the second signal follows the inverse of the clock signal.
Typical detection circuitry does not provide a means for quickly detecting both rising and filling transitions in an input clock signal. For example, the detection circuit may have a trip point adjusted to quickly detect a rising transition, but the detection of the falling transition will be offset by an equal amount in the opposite direction. The output signal(s) of the detection circuit, therefore, will be delayed in one signal transition. Further, where the buffer circuit produces complimentary output signals, the output signals are susceptible to skew. As such, circuitry operating in response to the output signals may require a buffer circuit to reduce the effects of the signal skew.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a detection circuit which quickly detects transitions in an input clock signal and reduces signal skew between output signals.